The field of the present invention pertains to semiconductor fabrication processing. More particularly, the present invention relates to a method and system for planarizing semiconductor wafers.
Most of the power and usefulness of today""s digital integrated circuit (IC) devices can be attributed to the increasing levels of integration. More and more components (resistors, diodes, transistors, and the like) are continually being integrated into the underlying chip, or IC. The starting material for typical ICs is very high purity silicon. The material is grown as a single crystal. It takes the shape of a solid cylinder. This crystal is then sawed (like a loaf of bread) to produce wafers typically 10 to 30 cm in diameter and 250 microns thick.
The geometry of the features of the IC components are commonly defined photographically through a process known as photolithography. Very fine surface geometries can be reproduced accurately by this technique. The photolithography process is used to define component regions and build up components one layer on top of another. Complex ICs can often have many different built up layers, each layer having components, each layer having differing interconnections, and each layer stacked on top of the previous layer. The resulting topography of these complex IC""s often resemble familiar terrestrial xe2x80x9cmountain ranges,xe2x80x9d with many xe2x80x9chillsxe2x80x9d and xe2x80x9cvalleysxe2x80x9d as the IC components are built up on the underlying surface of the silicon wafer.
In the photolithography process, a mask image, or pattern, defining the various components, is focused onto a photosensitive layer using ultraviolet light. The image is focused onto the surface using the optical means of the photolithography tool, and is imprinted into the photosensitive layer. To build ever smaller features, increasingly fine images must be focused onto the surface of the photosensitive layer, i.e., optical resolution must increase. As optical resolution increases, the depth of focus of the mask image correspondingly narrows. This is due to the narrow range in depth of focus imposed by the high numerical aperture lenses in the photolithography tool. This narrowing depth of focus is often the limiting factor in the degree of resolution obtainable, and thus, the smallest components obtainable using the photolithography tool. The extreme topography of complex ICs, the xe2x80x9chillsxe2x80x9d and xe2x80x9cvalleys,xe2x80x9d exaggerate the effects of decreasing depth of focus. Thus, in order to properly focus the mask image defining sub-micron geometries onto the photosensitive layer, a precisely flat surface is desired. The precisely flat (i.e., fully planarized) surface will allow for extremely small depths of focus, and in turn, allow the definition and subsequent fabrication of extremely small components.
Chemical mechanical polishing (CMP) is a preferred method of obtaining full planarization of a semiconductor wafer. It involves removing a sacrificial layer or portion of sacrificial layer of dielectric material using mechanical contact between the wafer and a moving polishing pad saturated with slurry. Polishing flattens out height differences, since high areas of topography (hills) are removed faster than areas of low topography (valleys). Polishing is the only technique with the capability of smoothing out topography over millimeter scale planarization distances leading to maximum angles of much less than one degree after polishing.
FIG. 1 shows a top view of a chemical mechanical polishing (CMP) machine 100 and FIG. 2 shows a side view of CMP machine 100. CMP machine 100 is fed semiconductor wafers to be polished. CMP machine 100 picks up the wafers with an arm 101 and places them onto a rotating polishing pad 102. Polishing pad 102 is made of a resilient material and is textured, often with a plurality of predetermined grooves 103, to aid the polishing process. Polishing pad 102 rotates on a platen 104 (not shown in FIG. 1), or turn table located beneath polishing pad 102, at a predetermined speed. A wafer 105 is held in place on polishing pad 102 within a carrier ring 112 that is connected to a carrier film 106 (not shown in FIG. 1) of arm 101. The lower surface of wafer 105 rests against polishing pad 102. The upper surface of wafer 105 is against the lower surface of carrier film 106 of arm 101. As polishing pad 102 rotates, arm 101 rotates the wafer 105 at a predetermined rate. Arm 101 forces wafer 105 into the polishing pad 102 with a predetermined amount of down force. CMP machine 100 also includes a slurry dispense arm 107 extending across the radius of polishing pad 102 which dispenses a flow of slurry onto polishing pad 102.
The slurry is a mixture of deionized water and polishing agents designed to chemically aid the smooth and predictable planarization of the wafer. The rotating action of both polishing pad 102 and wafer 105, in conjunction with the polishing action of the slurry, combine to planarize, or polish, wafer 105 at some nominal rate. This rate is referred to as the removal rate. A constant and predictable removal rate is important to the uniformity and throughput performance of the wafer fabrication process. The removal rate should be expedient, yet yield precisely planarized wafers, free from surface anomalies. If the removal rate is too slow, the number of planarized wafers produced in a given period of time decreases, hurting wafer throughput of the fabrication process. If the removal rate is too fast, the CMP planarization process will not be uniform across the surface of the wafers, hurting the yield of the fabrication process.
To aid in maintaining a stable removal rate, CMP machine 100 includes a conditioner assembly 120. Conditioner assembly 120 includes a conditioner arm 108, which extends across the radius of polishing pad 102. An end effector 109 is connected to conditioner arm 108. End effector 109 includes an abrasive conditioning disk 110 which is used to roughen the surface of polishing pad 102. Conditioning disk 110 is rotated by conditioner arm 108 and is translationally moved towards the center of polishing pad 102 and away from its center, such that conditioning disk 110 covers the radius of polishing pad 102. In so doing, conditioning disk 110 covers the surface area of polishing pad 102, as polishing pad 102 rotates. A polishing pad having a roughened surface has an increased number of micro-pits and gouges in its surface from conditioner assembly 120 and therefore produces a faster removal rate. This is due in part to the increase in slurry transfer to the surface of wafer 105 and the increase polishing by-product removal away from the surface of wafer 105. Without conditioning, the surface of polishing pad 102 is smoothed during the polishing process and removal rate decreases dramatically. Conditioner assembly 120 re-roughens the surface of polishing pad 102, thereby improving the removal rate by improving the transport of slurry and by-products.
As described above, the CMP process uses an abrasive slurry on a polishing pad. The polishing action of the slurry is comprised of an abrasive frictional component and a chemical component. The abrasive frictional component is due to the friction between the surface of the polishing pad, the surface of the wafer, and abrasive particles suspended in the slurry. The chemical component is due to the presence in the slurry of polishing agents which chemically interact with the material of the dielectric layer of wafer 105. The chemical component of the slurry is used to soften the surface of the dielectric layer to be polished, while the frictional component removes material from the surface of wafer 105.
Referring still to FIG. 1 and FIG. 2, the polishing action of the slurry determines the removal rate and removal rate uniformity, and thus, the effectiveness of the CMP process. As slurry is xe2x80x9cconsumedxe2x80x9d in the polishing process, the transport of fresh slurry to the surface of wafer 105 and the removal of polishing by-products away from the surface of wafer 105 becomes very important in maintaining the removal rate. Slurry transport is facilitated by the texture of the surface of polishing pad 102. This texture is comprised of both predefined grooves 103 and micro-pits that are manufactured into the surface of polishing pad 102 and the inherently rough surface of the material from which polishing pad 102 is made.
The slurry is typically transported by grooves 103 or pits of polishing pad 102 under the edges of wafer 105 as both polishing pad 102 and wafer 105 rotate. Consumed slurry and polishing by-products, in a similar manner, are also typically transported by grooves 103 or pits of polishing pad 102 away from the surface of wafer 105. As the polishing process continues, fresh slurry is continually dispensed onto the polishing pad from slurry dispense arm 107. The polishing process continues until wafer 105 is sufficiently planarized and removed from polishing pad 102.
There are several disadvantages associated with the CMP planarization process of semiconductor wafers described above. One of the main disadvantages is that a typical CMP process produces large amounts of liquid waste by-products (e.g., slurry, deionized water, and other chemicals). As such, a semiconductor device manufacturer incurs additional expenses in order to properly dispose of the waste by-products, recycle the waste by-products, or both. It should be appreciated that any of these options for handling the waste by-products of the CMP process can be expensive and are therefore disadvantageous to semiconductor manufacturers.
Another one of the main disadvantages associated with a conventional CMP process is that a typical water base slurry utilized during the CMP process negatively impacts the dielectric constant of some types of spin on glass materials. Such spin on glass materials include hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ). The spin on glass materials are used to fabricate semiconductor devices on semiconductor wafers. It should be appreciated that the slurry attacks some types of spin on glass materials on contact, thereby ruining the whole stack of the wafer. Therefore, typical CMP processes are ineffective for planarizing semiconductor wafers fabricated with some types of spin on glass materials.
Furthermore, there is another disadvantage associated with a typical CMP process. Specifically, the CMP process is not a very effective planarization process for organic polymers (e.g., carbon hydrogen components), which are used as low dielectric constant materials within semiconductor devices. One of the main reasons CMP is not very effective is that chemical components within typical slurries are unable to sufficiently soften organic polymers. As a result, it is difficult to remove the desired amount of an organic polymer.
Accordingly, what is desired is a system and method for planarizing semiconductor wafers which does not produce significant amounts of liquid waste by-products. Furthermore, what is desired is a system and method for effectively planarizing semiconductor wafers having spin on glass materials (e.g., HSQ and MSQ) deposited thereon. Moreover, what is desired is a system and method for effectively planarizing semiconductor wafers having organic polymers (e.g., carbon hydrogen) deposited thereon. The present invention provides these advantages. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.
The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas.
Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material. Once the chemical bonds are broken, reactive radicals within a plasma gas chemically react with the surface material thereby forming a gaseous species which is highly volatile. In other words, the plasma gas is used to remove previously mechanically polished material from the dielectric layer. Although these processes of mechanical and chemical removal of material are described separately, they would typically be occurring simultaneously. Subsequently, the newly formed gaseous species is removed from the vacuum planarization chamber. This process of removing material from the surface of the semiconductor wafer continues until the surface is sufficiently planarized. In this manner, the present embodiment provides a dry process for planarizing a surface of a semiconductor wafer. It should be appreciated that a process in accordance with the present invention has the capability of smoothing out topography over millimeter scale planarization distances, leading to maximum planarization angles of much less than one degree after the gas phase planarization process.
Specifically, one embodiment of the present invention includes a method for improving planarization of a semiconductor wafer. The method comprises the steps of placing a semiconductor wafer onto a polishing pad of a mechanical polishing machine. The semiconductor wafer includes a dielectric layer. Furthermore, the semiconductor wafer and the polishing pad are located within a vacuum chamber. Another step of the method involves forming a vacuum within the vacuum chamber. Subsequently, there is a step of weakening or breaking a plurality of chemical bonds of the dielectric layer of the semiconductor wafer through a mechanical action of frictionally moving the dielectric layer against a dry abrasive surface of the polishing pad. The step of breaking the plurality of chemical bonds results in material of the dielectric layer becoming amenable for chemical attack. Another step involves removing the material of the dielectric layer from the vacuum chamber utilizing a reactive gas. It should be appreciated that within the present embodiment the reactive gas can be ionized gas.